1. Field of the Invention
The invention relates to devices controlling a phase change storage element and methods thereof, wherein reliability of a phase change storage element is increased.
2. Description of the Related Art
Phase change storage elements are generally used in memory devices, named phase change memories (PCMs). The phase change storage element can switch between a crystalline state and an amorphous state. A write current is forced into the phase change storage element to vary its state. The state of the phase change storage element is dependent on the magnitude and the conduction period of the write current. When the write current has a great magnitude and a short conduction period, the phase change storage element is switched to the amorphous state and has great resistance. This condition is named ‘reset mode’, and is used in storing data ‘1’. When the write current has a low magnitude and a long conduction period, the phase change storage element is switched to the crystalline state and has low resistance. This condition is named ‘set mode’, and is used in storing data ‘0’.
To achieve large capacity, modern memory devices are usually composed of a plurality of memory banks. On a wafer, the memory banks may spread over a large area. Because of manufacturing process deviations, the different areas of a wafer may have different electronic characteristics, such that the phase change storage elements of different memory banks on a wafer may have different resistances when they are in the set mode.
In this specification, the ideal resistance of a phase change storage element in the set mode is named ‘ideal set mode resistance’. In a case where the ideal set mode resistance is 10K ohm, the resistance of a phase change storage element should be 10K ohm after being forced a write current for an ideal conduction period. However, because of manufacturing process deviations, some phase change storage elements may not be completely transformed into the set mode. As a result, the set mode resistance is increased to 15K ohm from 10K ohm, much greater than the ideal set mode resistance. Additionally, in other cases, because of manufacturing process deviations, some phase change storage elements may be too sensitive to the write current. As a result, the set mode resistance is decreased to 8K ohm from 10K ohm, much lower than the ideal set mode resistance.
Thus, novel techniques capable of equalizing the resistance of all phase change storage elements of all memory banks are called for.